This invention relates generally to a non-volatile memory and its operation, and, more specifically, to techniques for reducing disturbs during programming and reading operations.
The principles of the present invention have application to various types of non-volatile memories, those currently existing and those contemplated to use new technology being developed. Implementations of the present invention, however, are described with respect to a flash electrically-erasable and programmable read-only memory (EEPROM), wherein the storage elements are floating gates.
During the operation of a non-volatile memory, reading and writing of data in one storage unit will often disturb the data stored in other storage units of the memory. One source of these disturbs is the field effect coupling between adjacent floating gates as described in U.S. Pat. No. 5,867,429 of Jian Chen and Yupin Fong, which patent is incorporated herein in its entirety by this reference. The degree of this coupling is necessarily increasing as the sizes of memory cell arrays are being decreased as the result of improvements of integrated circuit manufacturing techniques. The problem occurs most pronouncedly between two sets of adjacent cells that have been programmed at different times. One set of cells is programmed to add a level of charge to their floating gates that corresponds to one set of data. After the second set of cells is programmed with a second set of data, the charge levels read from the floating gates of the first set of cells often appears to be different than programmed because of the effect of the charge on the second set of floating gates being coupled with the first. This is known as the Yupin effect. Aforementioned U.S. Pat. No. 5,867,429 suggests either physically isolating the two sets of floating gates from each other, or taking into account the effect of the charge on the second set of floating gates when reading that of the first. Additional techniques for reducing such disturbs are described in U.S. patent application Ser. No. 09/893,277, filed Jun. 27, 2001, by Jian Chen, Tomoharu Tanaka, Yupin Fong, and Khandker N. Quader and entitled xe2x80x9cOperating Techniques for Reducing Effects of Coupling Between Storage Elements of a Non-Volatile Memory Operated in Multiple Data Statesxe2x80x9d, which is incorporated herein in its entirety by this reference.
This effect and other sources of read and write disturbs are present in various types of flash EEPROM cell arrays. A NOR array of one design has its memory cells connected between adjacent bit (column) lines and control gates connected to word (row) lines. The individual cells contain either one floating gate transistor, with or without a select transistor formed in series with it, or two floating gate transistors separated by a single select transistor. Examples of such arrays and their use in storage systems are given in the following U.S. patents and pending applications of SanDisk Corporation that are incorporated herein in their entirety by this reference: U.S. Pat. Nos. 5,095,344, 5,172,338, 5,602,987, 5,663,901, 5,430,859, 5,657,332, 5,712,180, 5,890,192, and 6,151,248, and U.S. Ser. Nos. 09/505,555, filed Feb. 17, 2000, and 09/667,344, filed Sep. 22, 2000.
A NAND array of one design has a number of memory cells, such as 8, 16 or even 32, connected in series string between a bit line and a reference potential through select transistors at either end. Word lines are connected with control gates of cells in different series strings. Relevant examples of such arrays and their operation are given in the following U.S. patents and pending application of Toshiba that are incorporated herein in their entirety by this reference: U.S. Pat. Nos. 5,570,315, 5,774,397 and 6,046,935, and U.S. Ser. No. 09/667,610.
There are different mechanisms that can be used to program EEPROM memory cells. In the references incorporated above, NOR memory cells are commonly programmed by using hot electrons to tunnel through the tunneling oxide to the floating gate, whereas the NAND cells are typically programmed in a Nordheim-Fowler cold tunneling process. An advantage of Nordheim-Fowler tunneling is that it typically uses less power to program a cell; however, it also tends to be more prone to causing disturbs in non-selected cells when the control gate is biased at the high voltage, particularly when selected and non-selected bit-lines share word-lines, as in U.S. patent application Ser. No. 09/893,277 that is incorporated by reference above. The amount of disturb depends on the voltage difference between the control gate and the substrate. In the program case, the control gate is set at a programming of Vpgm=15-24 volts. In the read process, the voltage of the unselected gates are biased at a lower level, usually 4-5 volts. The effect of the read disturb is much less per read, but a cell experiences more read than programs so that the cumulative effect can still be non-negligible. In a NAND architecture, in both read and program operations the unselected word lines are biased to let the voltage pass to the selected cells in the NAND chains. The unselected cells are connected to unselected word lines biased at the high pass voltages and will consequently be subject to disturbs.
It is still most common in current commercial products for each floating gate to store a single bit of data by operating in a binary mode, where only two ranges of threshold levels of the floating gate transistors are defined as storage levels. The threshold levels of a floating gate transistor correspond to ranges of charge levels stored on their floating gates. In addition to shrinking the size of the memory arrays, the trend is to further increase the density of data storage of such memory arrays by storing more than one bit of data in each floating gate transistor. This is accomplished by defining more than two threshold levels as storage states for each floating gate transistor, four such states (2 bits of data per floating gate) now being included in commercial products. More storage states, such as 16 states per storage element, are contemplated. Each floating gate transistor has a certain total range (window) of threshold voltages in which it may practically be operated, and that range is divided into the number of states defined for it plus margins between the states to allow for them to be clearly differentiated from one another. In a multi-state nonvolatile memory, the threshold voltage ranges are often increased in comparison with single-bit memories in order to accommodate the all of the multi-states and their margins. Correspondingly, the voltages applied to the control gates during read and programming are correspondingly increased, resulting in more program and read disturbs.
A common operation of these types of non-volatile memories is to erase blocks of memory cells prior to reprogramming them. The cells within the block are then individually programmed out of erase into states represented by the incoming data being stored. Programming typically includes alternate application to a large number of memory cells in parallel of programming voltage pulses and a reading of their individual states to determine whether the individual cells have reached their intended levels. Programming is stopped for any cell that is verified to have reached its intended threshold level while programming of the other cells being programmed in parallel continues until all of those cells are programmed. When the number of storage states per storage element is increased, the time to perform the programming will usually be increased since the smaller voltage ranges for the individual states requires a greater precision of programming. This can have a significant adverse impact on the performance of the memory system.
The narrower ranges of the defined floating gate storage levels that result from multi-state operation increases the level of sensitivity of a first group of storage elements to the amount of charge stored on a later programmed second group of adjacent storage elements. When the first group is being read, for example, the charge on the second group can lead to errors in reading the states of the first group. The field coupled from the adjacent memory elements can shift the apparent state being read a sufficient amount to lead to an erroneous read of at least some bits of a group of stored data. If the number of erroneous bits is maintained within the capability of an error correction code (ECC), the errors are corrected but if the number of errors is typically larger than that, some other structural and/or operating technique(s) needs to be employed. The techniques described in aforementioned U.S. Pat. No. 5,867,429 are suitable for many arrays but it is desired to provide additional techniques to compensate for the read and write disturbs in nonvolatile memories.
The present invention presents a non-volatile memory having a plurality of erase units or blocks, where each block is divided into a plurality of parts sharing the same word lines to save on the row decoder area, but which can be read or programmed independently. An exemplary embodiment has blocks composed of a left half and a right half, where each part will accommodate one or more standard page (data transfer unit) sizes of 512 bytes of data. In the exemplary embodiment, the left and right portions of a block each have separate source lines, and separate sets of source and drain select lines. During the programming or reading of the left side, as an example, the right side can be biased to produce channel boosting to reduce data disturbs. In an alternate set of embodiments, the parts can have separate well structures.
To reduce the amount of disturb in both read and write processes, the present invention boosts the surface of the channel in the non-selected portion. In a exemplary embodiment, an initial voltage is supplied to the channel, after which select gate transistors will cut off the leakage path and make the channel floating, followed by ramping up the control gate voltage and boosting the substrate channel the subsequent operation. To allow the selected and non-selected portions of a block of the array to be biased independently, each portion has independently controllable select gate transistors and source lines.
Additional aspects, features and advantages of the present invention are included in the following description of exemplary embodiments, which description should be taken in conjunction with the accompanying drawings.